1. Field of the Invention
This invention relates to field-effect semiconductor devices and, more particularly, to field-effect semiconductor devices which can reduce the on-state source-drain saturation voltage.
2. Description of the Prior Art
As one type of the field-effect transistors that have heretofore been used, there is known a static induction transistor (hereinafter referred to as SIT). The SIT realizes the same characteristics as those of the triode in the form of a transistor. Japanese Laid-Open Patent Publication No. 64-51668 shows examples of the SIT structure.
FIG. 31 is a sectional view showing the structure of a prior art example. Illustrated in FIG. 31 is an SIT 200 which comprises a semiconductor substrate 201 having a recess with an n-type island semiconductor region 203 provided wherein via an insulation layer 202. In the following description, an n-type semiconductor region is referred to as n-type region, and a p-type semiconductor region is referred to as p-type region.
In the n-type region 203, an n.sup.+ -type source region 204 and an n.sup.+ -type drain region 205 are formed, and also a ring-like p-type gate region 206 is formed such as to surround the n.sup.+ -type source region 204. In the following description, an n.sup.+ -type region and a p.sup.+ -type region are referred to as a region where impurity concentration is high.
A source electrode 208, a drain electrode 209 and a gate electrode 211 are provided in ohmic connection to the n.sup.+ -type source region 204, the n.sup.+ -type drain region 205 and the p-type gate region 206 via contact holes 207a, 207b and 207c formed in an oxide insulation layer 207, respectively. Thus, as shown by dashed line 212, a drain-source current path is provided which extends through the n-type semiconductor region 203 from the n.sup.+ -type drain region 205 to the n.sup.+ -type source region 204. In this case, the drain-source current flows by bypassing the gate region 206, that is, it flows for a long distance through the high resistivity n-type region 203. Therefore, on-state source-drain saturation voltage is rather high.
It has been thought to reduce the on-state source-drain saturation voltage by forming an n.sup.+ -type buried region in the entire bottom of the n-type region 203 such that the source-drain current flows through this n.sup.+ -type buried region. However, where the n.sup.+ -type buried region is formed, it is required to form the n-type region 203 over the n.sup.+ -type buried region by using epitaxial techniques, thus leading to high cost of manufacture.
FIG. 32 shows a different prior art example which is shown in Japanese Laid-Open Patent Publication No. 62-174977. As shown in FIG. 32, a drain electrode 245C is formed on an insulating support substrate 240. An n.sup.+ -type drain region 245 of a high impurity concentration is formed on the drain electrode 245C. An n-type channel region 246 of a low impurity concentration is formed on the drain region 245. The top of the n-type channel region 246 has raised and recessed portions. Atop the raised portion, an n.sup.+ -type source region 243 of a high impurity concentration is formed. A source electrode 243C is formed on the n.sup.+ -type source region 243. On the side walls and bottom of the recessed portion, an undoped gate region 244 is formed. A gate electrode 244C is formed on the outer side of the gate region 244. With the semiconductor device having this structure, switching of the resistance between the source and drain regions 243 and 245 is obtainable by switching the potential applied to the gate electrode 244C.
While the above device is operable satisfactorily as a static induction transistor, its breakdown voltage basically greatly depends on the film thickness L of the channel region 246. Therefore, it is impossible to obtain sufficient breakdown voltage when the thickness L of the channel region 246 is thin. When the channel region 246 is formed by a method of forming a semiconductor layer, such as a SIMOX process, in which an Si layer is formed on an SiO.sub.2 insulation layer by oxygen ion implantation into an Si substrate and a subsequent high temperature annealing treatment, the thickness of the Si layer is thin. On the other hand, increasing the film thickness L to increase the breakdown voltage leads to an increase of the on-state source-drain saturation voltage.